Easy Start CPLD

Easy start CPLD kit has been designed to equip the fresh VLSI learners with fundamental concepts and gain confidence for advanced learning. The kit contains all required components to implement a small digital system using Xilinx programmable logic device. Your first step to experiment in the field of VLSI design.

Basic Configuration

Rapid Prototyping board for XC9572 or XC95108 – 84Pin CPLD
10 Pin FRC Header to configure onboard CPLD with External JTAG
Four 7-Segment CA Multiplexed LED Displays
8 Input Digital Logic Settings [Logic 0 / 1] set by 8 SPDT Slide switches
8 Input Trigger Settings using 8 push buttons – routed via inverters to reduce switch De-bounce
8 LEDs for easy logic state monitoring
2 Outputs ported to 2 Relays
1 Output ported to Buzzer
All port-pins available on 50-pin header – Expansion slot
Interchangeable Crystal Oscillator Blocks for different Osc. Frequency
Multi Frequency Clock generator module – X/2,4/8/16/32/64/128/256/512/1024/2048/4096. [X = Osc. Frequency]
Dip Switches on board to isolate any unused I/O pins from resources if desired
Current limit Resistors on all input / output pins to protect CPLD

The Xilinx Inc. is providing the software tools to design CPLD of XC9500 family series using WebPACK ISE. WebPACK ISE is available free-of-charge by registering to Xilinx on www.xilinx.com.

In case of XC9572-PC84, there are total 72 macrocells and 69 I/O pins
In case of XC95108-PC84, there are total 108 macrocells and 69 I/O pins. Macrocells are reconfigurable logic elements utilised for design implementation

Sample Programs

LED Blinking
Implementation Of logic gates
Implementation of binary adders and subtracters
JTAG Programmer
Random Sequence Generation with State Machine
Simple Process Control Logic using Relay
Detecting Key Combination on 7 Segment Display
4 x 7 Segment LED Counter
Simple security system using switches, relays and buzzer
BCD to 7 Seg decoder
BCD Up Counter
BCD Up / down counter
Binary up / down counter
Binary up / down counter